Ensuring plug-and-play interoperability for the growing CXL® ecosystem
Deploy CXL-attached memory at scale with confidence
- Rigorous testing of Leo Memory Controllers with industry-leading hosts, memory, and operating systems
- Comprehensive testing including PCIe electrical, memory, CXL® compliance and system level for end-to-end coverage
- Extensive testing with COSMOS software suite for Link, Fleet and RAS telemetry and diagnostics
Interop Bulletins
Interop Testing with Linux Operating Systems and Leo
Leo Interop with Intel Xeon 6 Processors
Interop Testing with Leo and DDR5-5600 RDIMMs
Interop Testing with CXL® 1.1 Host CPUs & DDR5 Memory
Hardware and Software Coverage
Example Tests
CXL® Compliance Tests
- PCIe Electrical Testing
- Transaction Layer Testing
- Arbitrator and Multiplexer
- Power Management Tests
- Reset and Initialization Tests
System & Memory Tests
- DDR Tests
- Stress Tests
- Traffic Tests
- Security Tests
- Reliability, Availability, and Serviceability
AI Just Outgrew The Server. The Rack-Scale Era Is Here.
The fastest path to AI Infrastructure 2.0 is through purpose-built solutions developed within open ecosystemsWe’ve crossed the Rubicon into AI Infrastructure 2.0. There’s no going back.The evidence is everywhere. The latest reasoning models demonstrate breakthrough capabilities through multi-step processing that demands an order of magnitude more compute than traditional inference….
Read moreAdvancing AI with AMD: Delivering Purpose-built Connectivity for Scale-up Architecture with UALink
Back in 2017, the founders of Astera Labs identified a looming bottleneck in data center infrastructure. While AI models were evolving at an unprecedented pace, traditional connectivity infrastructure wouldn’t keep up. From the beginning, Astera Labs set out with a clear mission: to deliver purpose-built connectivity solutions for the entire AI rack.Yesterday, we were honored to join…
Read moreHow PCIe® Retimers Keep High-Performance AI Infrastructure Connected
AI is accelerating at a pace few industries have ever witnessed. Every six months, model sizes are doubling, workloads are scaling across thousands of GPUs, and the demands on compute infrastructure are surging beyond anything imagined even a few years ago.At the rack level — and increasingly across entire data center systems — signals must travel longer distances, often over hundreds…
Read moreAstera Labs and Alchip Announce Strategic Partnership to Advance Silicon Ecosystem for AI Rack-Scale Connectivity
Hyperscalers benefit from seamless integration of purpose-built compute and connectivity solutions to rapidly deploy AI infrastructure at scale– SANTA CLARA, Calif. and TAIPEI, Taiwan – June 16, 2025 – Astera Labs, a leading provider of purpose-built connectivity solutions for AI and cloud infrastructure, and Alchip Technologies, the high-performance ASIC leader, today announced a…
Read moreAstera Labs Expands Collaboration with NVIDIA to Advance NVLink Fusion Ecosystem
NVLink connectivity solutions will further bolster Astera Labs’ Intelligent Connectivity Platform, expanding options for hyperscalers to deploy high-performance, scale-up networks – SANTA CLARA, CA, U.S. – May 19, 2025 – Astera Labs, Inc. (Nasdaq: ALAB), a global leader in semiconductor-based connectivity solutions for AI and cloud infrastructure, today announced it is collaborating…
Read moreAstera Labs Announces Financial Results for the First Quarter of Fiscal Year 2025
Record quarterly revenue of $159.4 million, up 13% QoQ and 144% YoYStrong demand for PCIe scale-up and Ethernet scale-out in custom ASIC platformsPCIe 6 connectivity portfolio poised to ramp in leading GPU-based rack-scale systems starting in Q2 – SANTA CLARA, CA, U.S. – May 6, 2025 – Astera Labs, Inc. (Nasdaq: ALAB), a global leader in semiconductor-based connectivity…
Read moreAstera Labs to Share Vision for Expanding Opportunities in AI Infrastructure with UALink
With broad industry support from 100+ companies in the UALink Consortium and the ratification of the UALink 200G 1.0 specification, UALink is emerging as the essential open standard for scale-up AI infrastructure – SANTA CLARA, CA, U.S. – May 5, 2025 – Astera Labs, Inc. (Nasdaq: ALAB), a global leader in semiconductor-based connectivity solutions for AI and cloud infrastructure,…
Read moreFirst Look Demo: Scorpio X-Series Fabric Switch
Scorpio X-Series Fabric Switches are architected to deliver the highest back-end bandwidth for AI scale-up (GPU-to-GPU communications.) Learn how Scorpio X-Series enables direct memory access across the fabric, allowing accelerators to read and write data to each other without PU intervention. This design significantly enhances data parallelism, reduces latency, and improves scalability for…
Read moreFirst Look Demo: Aries 6 Smart Gearbox
See the industry’s first purpose-built PCIe gearbox solution that intelligently bridges the performance gap between the latest PCIe 6 devices and existing PCIe 5 ecosystem.Learn how Aries 6 Gearbox solves the challenge of degraded-performance in mixed-generation systems, ensuring full utilization of high-speed lanes and accelerating the deployment of next-generation AI platforms while…
Read moreNVIDIA GTC 2025: End-to-End PCIe 6 Interop
At NVIDIA GTC 2025, Astera Labs showcased PCIe 6 end-to-end connectivity with our Scorpio P-Series Fabric Switch interconnected to Micron’s PCIe 6 SSD, an NVIDIA Blackwell GPU through our Aries 6 Smart Retimer, and an NVIDIA CX7 NIC card, with an Intel CPU connected on the upstream side. The demonstration shows how our Scorpio P-Series Fabric Switch can support mixed mode traffic, while…
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